Consumers continue to desire computer systems with higher performance and lower cost. To address higher performance requirements, computer chip designers have developed data processors having multiple processor cores along with a cache memory hierarchy on a single microprocessor chip. The caches in the cache hierarchy increase overall performance by reducing the average time required to access frequently used instructions and data. First level (L1) caches in the cache hierarchy are generally placed operationally close to a corresponding processor core. Typically, a processor core accesses its own dedicated L1 cache, while a last level cache (LLC) may be shared between more than one processor core and operates as the last cache between the processor cores and off-chip memory. The off-chip memory generally includes commercially available dynamic random access memory (DRAM) chips such as double data rate (DDR) synchronous DRAMs (SDRAMs), but may also include phase change memory (PCM).
PCM is an emerging form of non-volatile memory that provides certain advantages over other known types of memory. For example, PCM can be implemented with multiple bits in a single cell, and the data processor can take advantage of long-term persistent storage. Also, in contrast to DRAM, PCM does not require refresh operations since it is a non-volatile memory technology. More particularly, PCM technology is based on phase change material that has an amorphous phase having a high resistance, typically in megohms, and a crystalline phase having a low resistance, typically in kilohms. When the memory controller writes a logic zero to a memory cell, the PCM memory applies a large current to the associated cells for a short duration, in order to heat the PCM material and transform it to the amorphous phase. When the memory controller writes a logic one to a memory cell, the PCM memory applies a relatively smaller current to slowly heat the associated cells. However, the smaller current is applied to the cell for a longer duration to transform the PCM material to the crystalline phase. Thus, when the memory controller performs write back operations, the PCM consumes significant power based on the corresponding high programming voltage and current. The data processor also consumes more power and takes a longer time to complete write operations using PCM as the off-chip memory.
The cache controllers store new entries in their corresponding cache arrays in response to accesses by the processor cores. If a processor core has modified data stored in a cache line, the cache controller determines when to write the “dirty” cache line back to the off-chip memory according to its write back policy. For example, the cache controller may follow a write back on eviction policy. However, slow write back operations could degrade the overall performance of the microprocessor by causing the memory controller to inefficiently perform the write backs and possibly stalling the processor core, especially for example, when using PCM memory as the off-chip memory.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.